1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
The degree of integration of semiconductor integrated circuits, namely, integrated circuits using metal oxide semiconductor (MOS) transistors, has been increasing. The increasing degree of integration of such integrated circuits results in MOS transistors used therein having small sizes reaching nano-scale dimensions. Inverter circuits are fundamental circuits of digital circuits, and the increasing decrease in the size of MOS transistors included in inverter circuits causes difficulty in suppressing leak currents, leading to problems of reduced reliability due to hot carrier effects and of the reduction in the area of the circuits being prevented because of the requirements of the secure retention of necessary currents. To overcome the above problems, a surrounding gate transistor (SGT) having a structure in which a source, gate, and drain are arranged vertically with respect to a substrate and in which the gate surrounds an island-shaped semiconductor layer has been proposed (for example, Japanese Unexamined Patent Application Publications No. 2-71556, No. 2-188966, and No. 3-145761).
Further, an SGT manufacturing method has been proposed (Japanese Unexamined Patent Application Publication No. 2009-182317) which includes, in sequence, forming a pillar-shaped semiconductor layer, depositing a gate conductive film over the pillar-shaped semiconductor layer, planarizing the gate conductive film, etching back the gate conductive film to a desired length by using hard mask as a planarization stopper; forming an insulating film sidewall, patterning a gate line, and etching the gate conductive film. A hard mask is used as a planarization stopper, which can result in the uniformity of the gate length across a wafer surface. In this SGT manufacturing method which enables high yield with a high degree of integration and high performance, the upper surface of a gate electrode of an SGT is positioned lower than the upper surface of a pillar-shaped semiconductor layer.
Meanwhile, a complementary metal oxide semiconductor (CMOS) structure for increasing the degree of integration in a CMOS inverter has been proposed in which a gate electrode is formed around an island-shaped semiconductor to construct an n-channel MOS (NMOS) transistor and a cylindrical semiconductor layer is further formed around the gate electrode to construct a p-channel MOS (PMOS) transistor (Japanese Unexamined Patent Application Publication No. 3-225873). In the CMOS structure disclosed in Japanese Unexamined Patent Application Publication No. 3-225873, since the gate electrode is surrounded by the island-shaped semiconductor and the cylindrical semiconductor layer, a gate line made of the same material as the gate electrode is provided over the cylindrical semiconductor layer to apply voltage to the gate electrode. Therefore, as depicted in FIG. 6 in Japanese Unexamined Patent Application Publication No. 3-225873, the upper surface of the gate electrode is positioned higher than the upper surface of the cylindrical semiconductor layer. That is, it is difficult to use the manufacturing method disclosed in Japanese Unexamined Patent Application Publication No. 2009-182317 described above.
It is also known that in a static memory cell, the current driving force of a driver transistor is made double the current driving force of an access transistor to ensure operational stability (H. Kawasaki, M. Khater, M. Guillorn, N. Fuller, J. Chang, S. Kanakasabapathy, L. Chang, R. Muralidhar, K. Babich, Q. Yang, J. Ott, D. Klaus, E. Kratschmer, E. Sikorski, R. Miller, R. Viswanathan, Y. Zhang, J. Silverman, Q. Ouyang, A. Yagishita, M. Takayanagi, W. Haensch, and K. Ishimaru, “Demonstration of Highly Scaled FinFET SRAM Cells with High-κ/Metal Gate and Investigation of Characteristic Variability for the 32 nm node and beyond”, IEDM, pp. 237-240, 2008).
To construct a static memory cell using an NMOS SGT access transistor and also using a CMOS structure in which a gate electrode is formed around an island-shaped semiconductor layer to construct an NMOS SGT driver transistor and a cylindrical semiconductor layer is further formed around the gate electrode to construct a PMOS load transistor, two driver transistors are used because the gate width needs to be doubled in order to make the current driving force of a driver transistor double the current driving force of an access transistor to ensure operational stability. This leads to an increase in memory cell area.
Additionally, the increasing decrease in the size of static memory cells reduces the gate capacitance or diffusion layer capacitance of a MOS transistor to be connected to a storage node because of the reduction in dimensions. In this case, if the static memory cell is irradiated with radiation from the outside, electron-hole pairs are generated in a semiconductor substrate along the path of radiation, and at least the electrons or holes of the electron-hole pairs flow into a diffusion layer that forms the drain, causing data inversion. Thus, a soft-error phenomenon occurs in that data cannot be correctly held. The soft-error phenomenon has become a serious problem in recent static memory cells whose sizes have been reduced because as the decrease in the size of memory cells increases, the reduction in the gate capacitance or diffusion layer capacitance of the MOS transistor to be connected to the storage node becomes more noticeable than the electron-hole pairs generated by radiation. Therefore, it has been reported that a capacitor is formed in a storage node of a static memory cell to ensure sufficient electrical charges in the storage node so that the occurrence of soft errors can be avoided to ensure operational stability (Japanese Unexamined Patent Application Publication No. 2008-227344).